1. Field of the Invention
The invention relates to the field of metal-oxide-semiconductor (MOS) circuits compatible with emitter-coupled-logic (ECL) circuits.
2. Prior Art
It is a common practice to use more than a single circuit type, or logic type in an electrical system. For example, a metal-oxide-semiconductor (MOS) central processing unit may interface through buses with peripheral units adapted to receive transistor-transistor-logic (TTL) level signals. Often, MOS circuits include buffers which enable the circuits to receive TTL level signals and to provide output signals which are TTL compatible. Examples of TTL to MOS buffers are described in U.S. Pat. No. 4,048,518.
There have been some attempts to fabricate MOS circuits which are compatible with emitter-coupled-logic (ECL) circuits. An ECL compatible MOS memory is described in U.S. Pat. No. 3,938,109. One disadvantage to this memory is that it requires external generation of a reference potential used to assure proper sensing of the relatively small voltage swing of the ECL signal.
Other circuits for interfacing between different kinds of logic families are described in U.S. Pat. Nos. 3,916,215 and 4,135,103.
In addition to the above patents, a search by Applicant uncovered the following patents:
U.S. Pat. Nos. 3,622,812; 3,965,367; 3,976,892; 4,032,795; 4,147,940; 4,192,016; 4,229,670.
As will be seen, the present invention provides, integral with an MOS integrated circuit, input and output buffers which are ECL compatible.